University of Massachusetts at Amherst

• 1996, Ph.D. - Dissertation: "Low-Power Techniques for Global Communication in CMOS VLSI",
• 1994, M.S. in Electrical and Computer Engineering.

"Politehnica" University, Bucharest, Romania

• 1984, Diploma in Electronics and Communications (ElCom) - Thesis: "Fermat and Mersenne Number Theoretic Transforms on a Bit-Slice Architecture".

University of Virginia

• 1996 - present, Assistant Professor in the Electrical and Computer Engineering Department. Member of the Center for Semicustom Integrated Systems (CSIS). Started the High-Performance Low-Power (HPLP) VLSI laboratory. Research in low-power and high-performance VLSI, digital and mixed-signal circuits. Teaching EE 736 - Advanced VLSI Design ( Fall 1999, Spring 1997), EE 563 - Introduction to VLSI Design ( Fall 2000, Fall 1999, Fall 1998, Fall 1997, Fall 1996), EE 436 - Advanced Digital Design ( Spring 2000, Spring 1999, Spring 1998), EE 408 - Bluetooth CSIDC project ( Spring 2001), EE 363 - Digital Integrated Circuits ( Spring 2001).

IBM, Essex Junction, VT

• 2000 summer, Visiting Faculty in the ASIC Microelectronics Division of IBM. Developed low power circuits and methodology for ASICs.

Intel Corp., Portland, OR

• 1999 summer, Visiting Faculty in the Circuit Research Lab (CRL) of the Intel Microprocessor Research Lab (MRL). Developed high performance, low power circuit design techniques.

University of Massachusetts at Amherst

• 1991 - 1996, Graduate Research and Teaching Assistant in the Electrical and Computer Engineering Department. Research in low-power VLSI, robot-path planning, analog and mixed-signal circuits.

Atis-Uher, Ltd., Atlanta, GA

• 1993 and 1995, Senior Systems Engineer. Engineered for production a professional digital voice recorder based on an embedded PC with a custom parallel signal acquisition architecture. Developed a a novel group code recording (GCR) with low-DC component for digital recording and engineered for production a SCSI VHS-based digital recorder developed in cooperation with JVC Japan. Participated in technology transfer meeting with JVC in Tokyo, Japan.

Graphica Computer Corp., Tokyo, Japan

• 1991, R&D Engineer. Developed a SCSI-based RAID 3 embedded architecture for high-throughput applications in computer graphics using standard, off-the-shelf, hard drives in a parallel configuration. This RAID 3 approach was used in all systems subsequently developed at Graphica.

ITC - Research Institute for Computers, Bucharest, Romania

• 1984 - 1990, R&D Engineer. Contributed to the architecture definition for the I-106 minicomputer family. Involved with I/O system design, developed several embedded controllers for different disk and tape drive types.

Honors and awards

• 2001, associate editor for the IEEE Transactions on VLSI Systems,
• 2001, Honorable Mention with prof. Ron Williams and a student team in the "Second Annual Computer Society International Design Competition (CSIDC)" organized by the IEEE Computer Society,
• 2000, Honorable Mention with a student team in the "Cu Design Challenge" contest organized by the Semiconductor Research Corporation (SRC),
• 2000, Visiting Faculty in the IBM Microelectronics Division,
• 1999, Visiting Faculty in the Intel Microprocessor Research Lab (MRL),
• 1998, Senior member of the IEEE,
• 1997, NSF CAREER award for "Advances in Theory, Design Methods, and CAD for Low-Power VLSI",
• 1997, voted best project by the University SIG of the Mentor Users Group for "Schematic Driven Layout for Analog VLSI Design",
• 1997, Life member of Phi Kappa Phi,
• 1995/1996, Outstanding Teaching Assistant Award, University of Massachusetts at Amherst,
• 1996, membership in the Phi Kappa Phi and Sigma Xi honor societies,
• 1984, Graduated in top 2% (5th out of 250) from the Electronics and Communications (ElCom) Department at "Politehnica" University, Bucharest, Romania,
• 1980, 3rd honorary prize at the Annual Students Conference, Bucharest, Romania, for "Flow Graphs for Electrical Circuit Analysis", (with Ioan Tache).

Journal editorship

• Associate Editor for:
  • IEEE Transactions on VLSI Systems.

Journal paper reviews

• Regular reviewer for:
  • IEEE Transactions on VLSI Systems,
  • IEEE Transactions on CAD,
  • IEEE Transactions on Circuits and Systems,
  • IEE Electronics Letters.
  Have also reviewed papers for the IEEE Journal of Solid-State Circuits, the VLSI Journal and the Journal of VLSI Signal Processing.

Conference organization

• Technical committee member for the 2002 Design, Automation and Test in Europe (DATE) Conference, Paris, France,
• Technical committee member for the 2002 International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona,
• Technical committee member for the 2002 Great Lakes Symposium on VLSI (GLSVLSI), Binghamton, New York,
• Technical committee member for the 2001 International Symposium on Low Power Electronics and Design (ISLPED), Huntington Beach, California,
• Technical committee member for the 2000 International Symposium on Low Power Electronics and Design (ISLPED), Rapallo, Italy,
• Technical committee member for the 1999 International Symposium on Low Power Electronics and Design (ISLPED), San Diego, California,
• Publicity chair and technical committee member for the 1998 International Symposium on Low Power Electronics and Design (ISLPED), Monterey, California,
• Technical committee member for the 2001 14th IEEE ASIC/SOC Conference, Washington, DC,
• Technical committee member for the 2001 19th Conference on Advanced Research in VLSI, Salt Lake City, Utah,
• Technical committee member for the 2000 International Conference on VLSI Design, Calcutta, India,
• Technical committee member for the 1999 International Conference on VLSI Design, Goa, India,
• Technical committee member for the 1998 International Conference on VLSI Design, Chennai, India,
• Session Chair for the 1999 X IFIP International Conference on VLSI, Lisbon, Portugal,
• Organizer of special session on low-power at 1999 International Symposium on Signals, Circuits and Systems, Iasi, Romania.

Professional societies

• Faculty advisor for the IEEE student chapter at UVa,
• Campus representative for USENIX, the Advanced Computing Systems Association,
• Senior member of the IEEE, member of the ACM and USENIX.

Book section

1. Mircea R. Stan, Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O", in Low-power CMOS design edited by Anantha Chandrakasan, Robert Brodersen, IEEE Press, 1998.

Journals

1. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, V. De, "Dual-VT SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for High-Performance On-Chip Cache in 0.13 um Technology Generation", IEEE Transactions on VLSI Systems, in print.
2. Mircea R. Stan, "CMOS Circuits with Sub-Volt Supply Voltages", IEEE Design and Test of Computers, in print.
3. Alvar Dean, David Garrett, Mircea R. Stan and Sebastian Ventrone, "Low Power Techniques for ASICs", VLSI Design Journal, pp. 317-331, Jun. 2001.
4. Mircea R. Stan, "Low Power CMOS with Sub-Volt Supply Voltages", IEEE Transactions on VLSI Systems, pp. 394-400, Apr. 2001.
5. David Garrett and Mircea R. Stan, "Low Power Parallel Spread-Spectrum Correlator", IEE Proceedings on Circuits, Devices and Systems, pp. 191-196, Aug. 1999.
6. Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac "Long and Fast Up/Down Counters", IEEE Transactions on Computers, pp. 722-735, Jul. 1998.
7. Mircea R. Stan, Wayne P. Burleson, "Low-Power Encodings for Global Communication in CMOS VLSI", IEEE Transactions on VLSI Systems, pp. 444-455, Dec. 1997.
8. Mircea R. Stan, Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O", IEEE Transactions on VLSI Systems, pp. 49-58, March 1995.
9. M. Stan, W. Burleson, C. Connolly, R. Grupen, "Analog VLSI for Robot Path-Planning", Journal of VLSI Signal Processing, pp. 61-73, Jun. 1994.
10. Marco Barcella, Mircea R. Stan, "MTCMOS Flip-Flops with Outside Feedback", submitted to IEEE Journal of Solid-State Circuits.
11. Fatih Hamzaoglu, David Garrett, Mircea R. Stan, "Non-Manhattan Maze Routing", submitted to ACM Transactions on Design Automation of Electronic Systems (TODAES).
12. Fatih Hamzaoglu, Mircea R. Stan, "Split-Path Skewed (SPS) CMOS Buffer for High Performance and Low Power Applications", submitted to IEEE Transactions on Circuits and Systems II.
13. Mircea R. Stan, Anshul Bhargava, Matthew Ziegler, "Parallel Prefix Adders with Custom Improvements", submitted to IEEE Transactions on Computers.
14. Mircea R. Stan, "Duality of a Class of Codes for Low Power VLSI and Block Error Correcting Codes", submitted to IEE Proceedings - Computers and Digital Techniques.
15. David Garrett, Mircea R. Stan and Alvar Dean, "Clock Gating Techniques for ASICs", second revision submitted to IEEE Transactions on VLSI Systems.

Journal papers under preparation

1. Mircea R. Stan, "Any-Modulus Asynchronous Prescaler", to be submitted to IEEE Transactions on Circuits and Systems.
2. Mircea R. Stan, "Perfect 3-Limited-Weight Code for Low Power Buses", to be submitted to IEEE Transactions on Computers.
3. Mircea R. Stan, "Systolic Counters with Unique Zero State", to be submitted to IEEE Transactions on Circuits and Systems.
4. Joshua Garrett, Mircea R. Stan, "Temperature as a Variable in Energy-Delay Product Optimization", to be submitted to IEEE Transactions on VLSI.

Major Conferences and Symposia (refereed)

1. Mircea Stan, Anshul Bhargava, Matthew Ziegler, "Parallel Prefix Adders for High-Performance Datapaths", submitted to the Design, Automation and Test in Europe (DATE) Conference, Paris, France, Mar. 2002.
2. Mircea Stan, Avishek Panigrahi, "The Selective Pull-up (SP) Noise Immunity Scheme for Dynamic Circuits", submitted to the Design, Automation and Test in Europe (DATE) Conference, Paris, France, Mar. 2002.
3. K. Skadron, T. Abdelzaher, M. R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", submitted to HPCA 8: Conference on High Performance Computer Architecture, Cambridge, MA, Feb. 2002.
4. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, M. R. Stan, "Power Issues Related to Branch Prediction", submitted to HPCA 8: Conference on High Performance Computer Architecture, Cambridge, MA, Feb. 2002.
5. Matthew Ziegler, Mircea R. Stan, "Flexible IP Blocks for Customized Synthesis", ASIC/SOC 2001 Conference, Washington, DC, Sep. 2001.
6. David Garrett, Mircea R. Stan, "A 2.5Mb/s, 23mW SOVA Traceback Chip for Turbo Decoding Applications", ISCAS 2001: International Symposium on Circuits and Systems, Sydney, Australia, May, 2001.
7. Joshua Garrett, Mircea R. Stan, "Active Threshold Compensation Circuit for Improved Performance in Cooled CMOS Systems", ISCAS 2001: International Symposium on Circuits and Systems, Sydney, Australia, May, 2001.
8. Matthew Ziegler, Mircea R. Stan, "Optimal Logarithmic Adder Structures with a Fanout of Two for Minimizing the Area-Delay Product", ISCAS 2001: International Symposium on Circuits and Systems, Sydney, Australia, May, 2001.
9. Y. Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan, V. De, "Comparative Delay, Noise, and Energy of High-Performance Domino Adders with Stack Node Preconditioning (SNP)", Symposium VLSI Circuits, Honolulu, Hawaii, Jun. 2000.
10. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, V. De, "Dual-VT SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for High-Performance On-Chip Cache in 0.13 um Technology Generation", ISLPED '00: International Symposium on Low Power Electronics and Design, Rapallo, Italy, Jul. 2000.
11. David Garrett, Alvar Dean, Mircea R. Stan, "Challenges in Clock Gating for Low Power for ASIC Cores", ISLPED '99: International Symposium on Low Power Electronics and Design, San Diego, CA, Aug. 1999.
12. Mircea R. Stan, "Optimal Voltages and Sizing for Low Power", VLSI '99: The Twelfth International Conference on VLSI Design, pp. 428-433, Goa, India, Jan. 1999.
13. Mircea R. Stan, "Low-Threshold CMOS Circuits with Low Standby Current", ISLPED '98: International Symposium on Low Power Electronics and Design, pp. 97-99, Monterey, CA, Aug. 1998.
14. David Garrett, Mircea R. Stan, "Low-Power Architecture for the Soft-Output Viterbi Algorithm", ISLPED '98: International Symposium on Low Power Electronics and Design, pp. 262-267, Monterey, CA, Aug. 1998.
15. Mircea R. Stan, "Low Power Encodings and ECC Duals", ISIT '98: International Symposium on Information Theory, pp. 19, Boston, MA, Aug. 1998.
16. Abhimanyu Kolla, Mircea R. Stan, Erik Herzog, Suzanne Moenter, "A Planar Integrated Sensor Array for Neural Recordings", Asilomar Conference on Computers, Signals and Systems, Pacific Grove, CA, Nov. 1997.
17. David Garrett, Mircea R. Stan, "Power Reduction Techniques for a Spread Spectrum Correlator", ISLPED '97: International Symposium on Low Power Electronics and Design, pp. 225-230, Monterey, CA, Aug. 1997.
18. Mircea R. Stan, "Synchronous Up/Down Counter with Clock Period Independent of Counter Size", ARITH-13: Symposium on Computer Arithmetic, pp. 274-281, Asilomar, CA, July 1997.
19. Mircea R. Stan, Wayne P. Burleson, "Two-dimensional Codes for Low-Power", ISLPED '96: International Symposium on Low-Power Electronics and Design, pp. 335-340, Monterey, CA, Aug. 1996.
20. Mircea R. Stan, Wayne P. Burleson, "Analog VLSI for Robot Path-Planning", Asilomar Conference on Computers, Signals and Systems, Pacific Grove, CA, 1992.

Other Conferences, Symposia and Workshops (refereed)

1. Mircea R. Stan, "A Scaling Scenario for Nanoelectronic Technologies", Georgia Tech Conference on Nanoscience and Nanotechnology, Atlanta, GA, Sept. 2001.
2. Matthew Ziegler, Mircea R. Stan, "Silicon and Molecular Electronics in terms of Information Processing Density",
3. M. Ziegler, A. Spanberger, G. Pai, M. R. Stan, K. Skadron, "Dynamic Way Allocation for High Performance, Low Power Caches", PACT 2001: International Conference on Parallel Architectures and Compilation Techniques, WiP session, Barcelona, Spain, September 8-12, 2001.
4. Arnaud Forestier, Mircea R. Stan, "Limits to Voltage Scaling from a Low Power Perspective", XIII Symposium on Integrated Circuits and System Design, Brazil, Sept. 2000.
5. M. Holzer, A.J. Nijdam, A. Kolla, G. Block, M. Geusz, E. Herzog, M. R. Stan, T. Blalock, W.-K. Lye, Y. Zu, M. L. Reed, "Integrated Microelectrode Arrays for In Vitro Neuronal Recording" poster, Biomedical Engineering Society 2000 Annual Fall Meeting. Annals of Biomedical Engineering, Vol 28, Supplement 1.
6. Alvar Dean, Sebastian Ventrone, David Garrett, Mircea R. Stan, "C54XDSP ASIC Core Low Power Experiences", High Speed VLSI Power Workshop, IBM Research, Yorktown Heights, NY, Aug. 1999.
7. Arnaud Forestier, Mircea R. Stan, "Low-Power Four-Quadrant Multiplier using Dual-Gate Transistors", SCS '99: The International Symposium on Circuits and Systems, Iasi, Romania, Aug, 1999.
8. Mircea R. Stan, Rama R. Kotapally, Andrew Slutter, "Op-Amps as Firm Virtual Components for Systems-on-Chip", IWV '99: IEEE Workshop on VLSI, pp. 54-59, Orlando, Florida, Apr. 1999.
9. David Garrett, Joshua Garrett, Mircea R. Stan, "Low-Power Design Environment for MOSIS", MUG '97: Mentor Graphics Users' Group Conference, Portland, OR, Oct. 1997.
10. Mircea R. Stan, David Garrett, Abhimanyu Kolla, Zaid Salman, "Schematic Driven Layout Using the MOSIS Design Kit for Advanced Analog and Mixed-Signal Design", MUG '97: Mentor Graphics Users' Group Conference, Portland, OR, Oct. 1997.
11. Mircea R. Stan, Wayne P. Burleson, "Synchronous Up/Down Counter with Period Independent of Counter Size", poster at FPGA '96, Monterey, CA, Feb. 1996.
12. Mircea R. Stan, Wayne P. Burleson, "Low-power CMOS Clock Drivers", TAU '95: International Workshop on Timing Issues, pp. 149-156, Seattle, WA, Nov. 1995.
13. Mircea R. Stan, Wayne P. Burleson, "Coding a Terminated Bus for Low-Power", GLSVLSI '95: Great Lakes Symposium on VLSI, pp. 70-73, Buffalo, NY, March 1995.
14. Mircea R. Stan, Wayne P. Burleson, "Limited-Weight Codes for Low-Power I/O", IWLPD '94: International Workshop on Low Power Design, pp. 209-214, Napa, CA, April 1994.
15. Mircea R. Stan, Sorin Guiman, "Firmware for Intelligent Peripheral Controllers - a Case Study of Real-Time Programming for Embedded Systems", WRTP'89: 16th IFAC/IFIP Workshop on Real-Time Programming, Berlin, Germany, 1989.
16. Mircea R. Stan, "A New Structural Solution for Designing a PC Disk-Drive Controller", CONDINF '89: 13th Symp. on Informatics, Cluj, Romania, 1989.
17. Mircea R. Stan, Sorin Guiman, "Microprogrammed Structure for Interfacing High-Performance Disk Drives to a Minicomputer System", SCA '88: National Symposium for Computers and Automation, Timisoara, Romania, 1988.
18. Mircea R. Stan, Gabriel Mateescu, "Intelligent Microprogrammed Controllers for Streaming Tape and Performant Disk Drives", INFOTEC '88: Information Technology Advances in Computer Science Conference, Bucharest, Romania, 1988.

Professional publications

1. Mircea R. Stan, "An ST506/ST412 Compatible Disk Drive", Electronic Engineering, Morgan Grampian, pp. 18, Aug. 1993.
2. Mircea R. Stan, "Programmable Logic Decodes Optical Encoders", Electronic Engineering, Morgan Grampian, pp. 37-38, June 1992.
3. Mircea R. Stan, "Modified Moebius Divide-by-N Counter with a 50% Duty Cycle", Electronic Engineering, Morgan Grampian, pp. 30-32, Sept. 1991.
4. Mircea R. Stan, "Shift Register Generators for Circular FIFOs", Electronic Engineering, Morgan Grampian, pp. 26-27, Feb. 1991.
5. Mircea R. Stan, "DMA Control for the Q-Bus", Electronic Engineering, Morgan Grampian, pp. 33, April 1990.
6. Mircea R. Stan, "Conditional Skip Manipulates Clock", EDN, Cahners, pp. 228, Dec. 6, 1990.

Invited lectures

1. Mircea R. Stan, "Sub-Volt Circuits with Multiple and Adaptive Threshold Voltages", Invited Talk Workshop on Low Power Circuits, Arlington, VA, Oct. 2001.
2. "High-Performance Low-Power Buses", Invited Workshop (with C.K. Ken Yang, UCLA), ASIC/SOC 2000, Washington, DC, Sep. 16, 2000.
3. "Low-Power Techniques in CMOS", Invited Seminar (with Wayne Burleson, ECE Dept., UMass/Amherst), Digital Semiconductor (currently Compaq), Hudson, MA, Nov. 16, 1995.
4. "Low Power Computing with I/0 Encoding", CS Department Graduate Seminar, SUNY at Binghamton, NY, March 17, 1995.

Patent applications

1. Mircea R. Stan, James Jasmin, "Multi-Threshold CMOS flip-flop with outside feedback", 2001, IBM.
2. Mircea R. Stan, Vivek De, "Dynamic CMOS Circuits with Individually Adjustable Noise Immunity", 1999, Intel.
3. David Garrett, Alvar Dean, Mircea R. Stan, "Methods for Improving the Efficiency of Clock Gating within Low Power Clock Trees", 1998, IBM.

Patent disclosures

1. Mircea R. Stan, "Parallel algorithm and structure for decoding parallel or serial concatenated codes (Turbo codes), 2000, UVa.
2. Mircea R. Stan, Suzanne Moenter, Abhimanyu Kolla, Erik Herzog, Gene Block, Alan Batson, Michael Geusz, "Addressable Array of Microelectrodes with Embedded Electronics for Neural Recording", 1998, UVa.

Published reviews

1. Book review (June 1996 issue of ACM Computing Reviews) of "AS/400 Security in a Client/Server Environment" by J. S. Park.
2. Journal paper review (June 1996 issue of ACM Computing Reviews) of "A design system for on-chip oversampling A/D interfaces" by M. F. Mar and R. Brodersen.
3. Journal paper review (Aug. 1996 issue of ACM Computing Reviews) of "A simplified design strategy for mapping image processing algorithms on a SIMD torus" by G. Seetharaman.
4. Book review (Feb. 1996 issue of ACM Computing Reviews) of "A Guide to VHDL Syntax: Based on the New IEEE Std 1076-1993" by J. Bhasker.
5. Journal paper review (Feb. 1996 issue of ACM Computing Reviews) of "Set-associative cache simulation using generalized binomial trees" by R. A. Sugumar and S. G. Abraham.
6. Comparative review (March 1996 issue of ACM Computing Reviews) of 6 VHDL books: "Circuit Synthesis with VHDL" by R. Airiau, J.-M. Berge and V. Olive, "Structured Logic Design with VHDL" by J. R. Armstrong and F. G. Gray, "VHDL Programming with Advanced Topics" by L. Baker, "A VHDL primer" by J. Bhasker, "A Designer's Guide to VHDL Synthesis" by D. E. Ott and T. J. Wilderotter and "VHDL" by D. L. Perry.
7. Journal paper review (Dec. 1995 issue of ACM Computing Reviews) of "Using visual texture for information display" by C. Ware and W. Knight.
8. Journal paper review (Mar. 1995 issue of ACM Computing Reviews) of "Pulse stream VLSI neural networks" by A. F. Murray, S. Churcher, A. Hamilton, A. J. Andrew.
9. Book review (Feb. 1995 issue of ACM Computing Reviews) of "Digital Design using ABEL" by D. Pellerin and M. Holley.
10. Book review (Nov. 1994 issue of ACM Computing Reviews) of "Discrete Iterated Function Systems" by M. Perrugia.
11. Book review (Oct. 1994 issue of ACM Computing Reviews) of "Contemporary Logic Design" by Randy H. Katz.
12. Book review (Jul. 1994 issue of ACM Computing Reviews) of "PSpice with Circuit Analysis" by F. Monssen.
13. Journal paper review (Jul. 1994 issue of ACM Computing Reviews) of "Reliability, reconfiguration, and spare allocation issues in binary-tree architectures based on multiple-level redundancy" by Y.-Y. Chen and S. J. Upadhyaya.
14. Book review (Jan. 1994 issue of ACM Computing Reviews) of "An Introduction to Systolic Algorithm Design" by G. M. Megson.
15. Book review (Dec. 1993 issue of ACM Computing Reviews) of "A Contour-Oriented Approach to Shape Analysis" by P. J. van Otterloo.
16. Book review (Sep. 1993 issue of ACM Computing Reviews) of "Circuit Design for CMOS VLSI" by J. P. Uyemura.
17. Journal paper review (Oct. 1992 issue of ACM Computing Reviews) of "VLSI implementation of a stochastic database machine for relational algebra and hashing" by L. M. Delcambre, M. A. Bayoumi and K. M. Elleithy.
18. Special issue review (Jul. 1993 issue of ACM Computing Reviews) of the April, 1992 IEEE Computer Journal special issue on Wafer-Scale Integration (WSI).
19. Book review (Apr. 1993 issue of ACM Computing Reviews) of "Representations of Musical Signals" by G. de Poli and A. Piccialli.
20. Book review (Dec. 1990 issue of ACM Computing Reviews) of "Understanding Digital Electronics" by M. J. Sanfilipo.

University of Virginia

• Faculty advisor for the IEEE student chapter at UVa,
• University of Virginia Campus representative for USENIX, the Advanced Computing Systems Association.

School of Engineering

• Common Reading Experience committee member,
• Computing Environment committee member.

Electrical and Computer Engineering Department

• Computing Resources Committee chair,
• Undergraduate Committee member,
• Eminent Speakers Committee member.

Awarded proposals

• "CCR: Small-Scale Dynamic Reconfigurability for Large-Scale Benefits", Co-PI (PI prof. John Lach, other Co-PI prof. Kevin Skadron), NSF, $400,000 for 3 years.
• "Sub-Volt CMOS circuits with reduced leakage", PI, Intel Corp., Nov. 1999, $125,880 for 3 years.
• "Low Power Design Techniques for ASIC DSP Cores", PI, IBM Corp., Jan. 1999, $70,000 for 1 year.
• "Advances in Theory, Design Methods, and CAD for Low-Power VLSI", PI, NSF CAREER award MIP-9703440, May 14, 1997, $250,000 for 5 years.
• "VLSI Design for Low Power", PI, NSF REU award, $5,000,
• "Low Power Library for Mentor Tools", PI, NSF REU award MIP-9743342, Aug. 27, 1997, $5,000.
• "Interfacing biological entities in-vitro with electronics: a CMOS integrated electrode array", Co-PI (PI Dr. Erik Herzog, Biology Dept.). NIH Shannon award, Sep. 1998, $100,000 for 2 years,
• "Schematic Driven Layout for Analog VLSI Design", PI, Mentor Graphics Corp., Jul. 9, 1997, $10,000.

Pending Proposals

• "Mixed CMOS/Nano Integrated Circuits - Analysis and Design", PI (Co-PIs are prof. James Aylor and prof. John Bean), SRC, $40,000 for 1 year.

Gifts

• $57,000 from Lucent for "Concatenated Coding for Wireless Array Systems" (with prof. Stephen Wilson).
• $8,000 unrestricted gift from SRC/Novellus for supporting the HPLP research program.
• 9 Dell PC workstations from Intel Corp. for the High Performance Low Power (HPLP) lab.

Ph.D.

• awarded:
  1. David Garrett, PhD dissertation: "Power Reduction Techniques for VLSI Signal Processing Architectures", 2000, now with Lucent Bell Labs, Sydney, Australia.
• in progress:
  1. Fatih Hamzaoglu, research in high-performance digital circuit.
  2. Hao Zhang, research in architectures for wireless communications.
  3. Yan Zhang, research in low power circuits.
  4. William Cy Wilson (NASA Langley), research in SOI, nanoelectronics.

Master of Science

• awarded:
  1. Joshua Garrett, MS thesis: "Temperature Analysis and Optimizations in High-Performance Low-Power VLSI", 2001, now a PhD student at UC Berkeley.
  2. Avishek Panigrahi, MS thesis: "Noise analysis, immunity in high performance VLSI", 2001, now with MIPS Technologies, Mountain View, CA.
  3. Anshul Bhargava, MS thesis: "Optimizations and Analyses for High Speed VLSI Circuits", 2001, now with MIPS Technologies, Mountain View, CA.
  4. Arnaud Forestier, MS thesis: "Transistor and Circuit Optimization in VLSI Design", 1999, now with Intel, Seattle, WA.
  5. Abhimanyu Kolla, MS thesis: "Design and Implementation of an Integrated Multimicroelectrode Array for In-Vitro Neuronal Recording", 1998, now with Intel, Seattle, WA.
• in progress:
  1. Garrett Rose.
  2. Wei Huang.
  3. Matthew Ziegler.
  4. Marco Barcella.

Undergraduate Students

1. Khanh Vu, senior thesis: "Optimizations for Copper Interconnect", 2001.
2. Jay Ring, senior thesis: "A Stochastic Implementation of a Digital Neural Network", 2001.
3. David Matthes, senior thesis: "High performance circuit design for a data path", 2000.
4. Justin Strock, senior thesis: "Using Peltier Coolers to Decrease Power Consumption in Integrated Circuits", 2000.
5. Paul Merolla, senior thesis: "Optimization of a multi-level inductor on a 0,18um process", 2000.
6. Frank Van Deman, senior thesis: "Development of a Palm Pilot based wearable computer", 2000.
7. Ryan Gates, senior thesis: Design, layout and simulation of a bi-directional shift register for use in a linear feedback shift register", 1999.
8. Paul Lappas, senior thesis: "Distributed memory M.I.M.D. architectures: design of a message-passing interface for the 35VEE8 processor", 1998.
9. Roger Lee, senior thesis: "State of the art report on non-volatile memory", 1999.
10. Douglas Madory, senior thesis: "Wearable computing", 1999.
11. Sung Moon, senior thesis: "CMOS transistor design: building an array multiplier using donut-shaped transistor design to reduce power consumption", 1999.
12. Jonathan Powers, senior thesis: "Design, vieification, and testing of a bidirectional shift register", 1999.
13. Andrew Slutter, senior thesis: "Development of a wearable computer system prototype emphasizing low coast and power consumption", 1999.
14. Timothy Tan, senior thesis: "CMOS transistor design: building an array multiplier using the donut-shaped transistor design to reduce power consumption", 1999.
15. Eric Ward, senior thesis: "Design of an EPROM", 1999.
16. Arash Afrashtech, senior thesis: "Comparative analysis of ATM, FDDI, and Fast Ethernet in today's LAN", 1998.
17. Darin Anderson, senior thesis: "Application of configurable computing techniques to general computing domains", 1998.
18. Christopher Cassatt, senior thesis: "Cache coherency in shared memory multiprocessors", 1998.
19. Loun-Loun Chua, senior thesis: "Adventures in microprocessor design: the 35VEE8", 1998.
20. Christopher Collins, senior thesis: "Cache design: improved microprocessor performance through a tri-segmented integrated cache", 1998.
21. Marc Monfalcone, senior thesis: "Design of the 35VEE8 microprocessor at the transistor level", 1998.
22. Michael Storrs, senior thesis: "Design and simulation of a superscalar processor", 1998.
23. Andrew Sugermeyer, senior thesis: "Frequency-adjustable digital guitar tuner: design and implementation", 1998.
24. Jennifer Wilhelmi, senior thesis: Microprocessor design: two-phase clocking in the 35VEE8 microprocessor", 1998.
25. David Wilson, senior thesis: "35VEE8 processor: eliminating the stack", 1998.
26. David Witter, senior thesis: "Adding floating-point operations to the 35VEE8 processor", 1998.
27. John W. Walker, senior thesis: "Talisman Testing and Evaluation Software (TalEval): Future trends in hardware/software codesign", 1997.

Exchange Students

1. Paolo Re, Italy, 2001.
2. Gregory Petit Dufrenoy, Belgium, technical report: "Sigma-Delta Modulator", 2000.
3. Alain Dannaoui, Switzerland, technical report: "Turbo Codes with reduced latency", 1998.

Ph.D. Dissertation Committee

1. David Garrett, "Power reduction techniques for VLSI signal processing architectures", 2000.
2. Munevver Kaya, "Flexible latency concatenated low complexity codes", 2000.
3. Wuping Chen, "Wrist sensor for warfighter status monitor", 2000.
4. Eric K. Hall, "Design and implementation of stream-oriented turbo codes", 1999.
5. Ronald Hayne, "Behavioral fault modeling in a VHDL synthesis environment", 1999.
6. Robert McGraw, "A system-level methodology and design environment for cycle-based systems", 1997.

M.S. Thesis Committee

1. Joshua Garrett, "Temperature Analysis and Optimizations in High-Performance Low-Power VLSI", 2001.
2. Avishek Panigrahi, "Noise analysis, immunity in high performance VLSI", 2001.
3. Anshul Bhargava, "Optimizations and Analyses for High Speed VLSI Circuits", 2001.
4. Arnaud Forestier, "Transistor and Circuit Optimization in VLSI Design", 1999.
5. Sreekanth Nallagatla, "Design of a GaAs integrated circuit for high frequency transceiver applications", 1998.
6. Abhimanyu Kolla, "Design and Implementation of an Integrated Multimicroelectrode Array for In-Vitro Neuronal Recording", 1998.