Electric Tutorial 6 – Putting it all together

(Based on material created by David Harris at Harvey Mudd college)


In this final tutorial, you will assemble and simulate your entire MIPS microprocessor!  You will first put together the top-level schematic and simulate that it executes MIPS instructions properly.  You will then assemble the layout and check that it is clean and matches the schematics.  Finally, you will generate a pad frame to connect your processor to the external world and verify that your system works in the pad frame.

1.   Top-Level Schematic Simulation


Copy your previous library for this tutorial. Look at the top-level mips cell that includes your datapath, alucontrol, and controller icons.  The system has the exported inputs and outputs given in Table 1. Notice that the internal wires and icons are also named to simplify debugging.











Table 1: MIPS Processor Inputs & Outputs

To demonstrate basic functionality of your microprocessor, you will simulate the processor running the mipstest.asm test program from Appendix A.10. Recall that you have developed a multi-cycle processor, so each instruction will require several steps.  A mips_sol.cmd file has been provided for you (download from class web page) with the commands to simulate the most of the instructions. Instructions 3 and 4 are missing.  Add them to the command file with the appropriate assertions. 


The IRSIM simulator uses a parameter file to determine the threshold for low and high voltages.  The threshold may have to be tightened from its default value for the memories to simulate properly.  Look at the lib\scmos0.3.prm file in the Electric directory.  Check that lowthresh and highthresh are 0.45 and 0.55, respectively; if they are not, change them.  Simulate the mips{sch} to prove that it works correctly.

2.   Top-Level Layout


Create a new layout in the library named mips.  In this top-level cell, place your datapath, alucontrol, and controller so that they will be easy to connect.  Wire together the modules.  Don’t forget to connect power and ground with fat wires and arrays of vias to handle the higher levels of current that may flow!  You will avoid creating a rats nest of wiring if you systematically reserve metal2 for vertical lines and metal1 for horizontal lines.  You may wish to consider placing a large number of long horizontal wires between the datapath and the controller/alucontrol, then dropping vertical lines in a systematic fashion to connect the blocks together.


Export all the inputs and outputs.  Label the internal signals.  Be sure all your labels and exports agree with the schematic.


Verify that your layout passes DRC (except the controller), ERC, and network compares with the schematic.  Be sure to run NCC twice, once in recursive mode and the other time in expand hierarchy mode.  Fix any problems that might arise.  As usual, simulating may catch problems that are difficult to isolate with NCC.

3.   Pad Frame Assembly


The tiny transistors on a chip must eventually be attached to the external world with a pad frame.  A pad frame consists of metal pads about 100 microns square; these pads are large enough to be attached to the package during manufacturing with thin gold bonding wires.  Each pad also contains large transistors to drive the relatively enormous capacitances of the external environment. 


Electric provides a handy pad frame generator that automatically assembles a pad frame for you from a library.  To use the pad frame generator, you need your library, a pad library, and a pad arrangement file.  The pad library is named muddpads11_ami05.elib.  Two pad arrangement files, mips_sch.arr and mips_lay.arr are also in the class directory.  Look at one of the pad arrangement files.  It defines the library in which the pad frame is stored, the name of the  cell to generate, and the name of your top-level design.  It then contains a list of each pad for the system.


Use the Tools • Generation • Pad Frame command and choose the mips_sch.arr file.  This will create a new facet called chip{sch} with generic unrouted arcs connecting the pads to the mips core.  Inspect the padframe to be sure it looks reasonable.


Opening the muddpads11_ami05 library will leave you with two libraries open.  Note that the Edit Facet dialog has a drop-down list of open libraries to help you navigate among the libraries. You may also find the File • Change Current Library command to be useful to switch between default libraries.


Now you must connect power and ground for the pads together.  Each pad has a VDD and a GND export on both edges that must be connected to the adjacent pad.  You could manually create all the connections yourself, but this is tedious.  Electric has a convenient function called Autostitch that connects two cells that have overlapping exports.  Select everything with the Select All command.  Then choose Tools • Routing • Autostitch Highlighted Now to automatically connect all the overlapping VDD and GND exports in the pads.


Repeat the process for the layout using mips_lay.arr.  Autostitch power and ground again.  Also connect power and ground between the pad frame and core; otherwise ERC will complain. In a real design you would need to delete the generic unrouted arcs in the layout and replace them with real metal lines.  This is called global routing and is sufficiently tedious that it is usually done with an automatic routing tool.  We don’t have one, so in this lab you may skip that step rather than do it by hand.  Your completed chip should resemble Figure 1.61 from CMOS VLSI Design. The overall layout is so big that Electric may display it in hashed form on the screen.  To see the contents, use the Facet • Facet Options • Hash facets when scale is more than 8 lambda per pixel.


Do a thorough final check on the top-level chip layout using the following steps and fix any errors:


1.      Info • Check and Repair Libraries

Makes sure library is stable before verification proceeds.

2.      Tools • DRC • DRC Options: Clear valid DRC dates

Check that alternate contact rules are selected and 3 layer submicron rules are used.

3.      Tools • DRC • Hierarchical Check

4.      Tools • Network • Network Options:

Recurse Through Hierarchy

Select Ignore Power and Ground and Check Sizes and Export Names

Do NCC Now

(repeat with Expand Hierarchy rather than Recurse to be paranoid)

5.      Tools • Electrical Rules • Analyze Wells (this may take a while)

6.      Simulate the chip layout from the mips.cmd command file.  This command file would also be used to test your chip after it is manufactured.

4.   Tapeout


The final step in designing a chip is creating a file containing the geometry needed by the vendor to manufacture masks.  Once upon a time these files were written to magnetic tape, and the process is still known as tapeout.  The two popular output formats are CIF and GDS; we will use CIF (the Caltech Interchange Format) because it is a human-readable text file and thus easier to inspect for problems than the binary GDS format. To write a CIF file:


1.      File • IO Options • CIF Options:

            Check Output Instantiates Top Level

            Select Show Resolution Errors

            Output resolution 0.5

2.      File • Export • CIF


Look at the CIF file in a text editor.  You should be able to identify the various cells.  Each cell contains boxes (rectangles) for each layer.  For example, the CMF layer is first-level metal and the CWN is n-well.


Electric may issue warnings about obscured facet exports; these may be ignored.  However, if you receive any resolution errors, try to fix them.  These occur if the elements of the design are not all on a 0.5 lambda grid and usually indicates sloppy layout practices such as not using facet centers or not drawing on grid.


Electric will report a MOSIS Cyclical Redundancy Check (CRC) code to ensure your CIF transmits correctly.  Record the two numbers indicating checksum and count, respectively.

5.   Summary


If you have successfully completed the tutorial, congratulations! You have designed, assembled, and tested your own microprocessor! You now are familiar with the major aspects of custom CMOS VLSI design:


·         Leaf cell design

·         Datapath design and assembly

·         Hardware specification with Verilog

·         Standard cell synthesis and place & route

·         Top-level system assembly

·         Pad frame generation and routing

·         Switch-level simulation and logic debug

·         Design Rule Checking

·         Electrical Rule Checking

·         Network compare and debug of mismatched networks


You will put these skills to use as you proceed with your final project!