Electric Tutorial 2 – Transient behavior

 

 

(Based mostly on material created by David Harris at Harvey Mudd college)

 

This tutorial guides you through the design of a 2-input NAND gate. You will draw and simulate schematics. Using your NAND gate and an inverter, you’ll design a 2-input AND gate.

 

1.   Schematic Entry

 

Your first task is to create a schematic for a 2-input NAND gate. Each design is kept in a facet; for example, your schematic will be in the nand2{sch} facet, while your layout will eventually go in the nand2{lay} facet and your AND gate will go in the and2{sch} facet. Choose File · Open Library to open your Tutorial1_xx library. Save the library as Tutorial2_xx. Choose Facet · Edit Facet to bring up the Facet dialog. Click New Facet. Enter nand2 as the facet name and schematic as the view. A new editing window will appear with the title Tutorial2_xx:nand2{sch} indicating the library, facet name, and view.

 

Electric defines various technologies for schematics and layout. To draw transistor-level schematics, you will need to select the Analog Schematic technology by choosing Technology · Change Current Technology and selecting the schematic, analog technology. This technology file contains basic circuit elements such as transistors, resistors, capacitors, and power and ground.

 

Your goal is to draw a gate like the one shown in Figure 1. Choose Windows · Toggle Grid to turn on a grid to help you align objects. Left-click on an nMOS transistor symbol in the components menu on the left side of the screen. Left-click on your schematic window to drop the transistor into your layout. Repeat until you have two nMOS transistors, two pMOS transistors, the circular power symbol, and the triangular ground symbol arranged on the page. You may move the objects around by left-clicking and dragging. The transistors default to a width/length value of 2/2. Double-click on the pMOS transistor and change its width to 12. Recall that nMOS transistors are roughly twice as strong as pMOS transistors. So a single nMOS transistor would only have to be 6 wide. However, because the nMOS transistors are in series, they should also be 12 wide.

 

Figure 1: nand2{sch}

 

Now, make the connections. Left-click on a port such as the gate, source, or drain of a transistor. Right-click on another port to create a wire connecting the ports. Continue until all the blue wiring is completed.

 

Finally, you will need to provide exports defining inputs and outputs of the facet. Left click on the end of a wire where you need to create the export for input a. You should see a small square box highlighted at the end of the wire. If the entire wire is highlighted, you clicked on the middle of the wire instead of the end, so try again. Once you have selected the end of the wire, choose Export · Create Export. Give your export the name a. Give it the characteristic Input. Repeat with the other input b. Export y as an Output.

 

Use File · Save (Ctrl-s) to save your library. Get into the habit of saving often because Electric crashes fairly often. Also, learn the keyboard shortcuts for the commands you use frequently.

2.   Switch-Level Simulation

 

Our next step is to simulate the schematic to ensure it is correct. Electric has two built-in switch-level simulators: IRSIM and ALS.  ALS is buggy, so we will use IRSIM.  IRSIM treats transistors as switches that may be ON or OFF; it also understands resistance and capacitance based on transistor sizes and crudely estimates switching delays.

 

First select Tools · Simulation (Built-in) · Simulation Options. Make sure that IRSIM is selected for Simulation engine. Check that the scmos0.3.prm parameter file is selected; this contains resistance and capacitance data for the technology we are using.  Start the simulation by selecting Tools · Simulation (Built-in) · Simulate. A waveform window will appear listing each of the nets in your design. If you created your exports properly, you will see nets for a, b, and y, as shown in Figure 2. You will also see an unnamed nets for the node between the series nMOS transistors; in the figure it is named net3.

 

The simulator has two vertical white cursors. The primary cursor with no x is used to create stimulus. Click and drag the cursor near the left edge (near time 0). Click on the a input in the simulation window and press h or 1 to drive the input high. Drag the cursor to some later time. Click on the b input and press h to drive it high. Use the l or 0 key sometime later to drive a and b back low, as shown in the figure. Check that the y output matches the behavior you would expect for a NAND2 gate. If it does not, fix the bug in your schematic and resimulate.

 

The secondary cursor with an x is only used to measure delays relative to the first cursor.  You will find that unloaded gate delays are under 100 ps.  Gate delay depends on the capacitance being driven, so attaching a realistic load will slow the gate.

 

Use the Windows · Adjust Position · Tile Vertically command to arrange the windows so that you can see both the simulation window and your schematic at the same time.  Watch the color-coding of the wires in the schematic change as you drag the primary cursor back and forth. On the schematic, magenta indicates high, blue indicates low, and black indicates x, an illegal value. When a signal is selected in the waveform window, the corresponding net will be highlighted on the schematic. Similarly, when a net is selected in the schematic then its waveform representation will be highlighted. Watching the voltage levels change on the schematic is helpful for debugging problems. Study your simulation and determine why the node between the two nMOS transistors behaves as it does. A thick purple bar means that the state is floating, undefined, or could not be made into a definite logic level.

 

Figure 2: Simulation of nand2{sch}

 

Make a habit of simulating each facet after you draw it so you catch errors while the design is fresh in your mind.

 

Electric cannot print waveforms directly.  To print your simulation results, press the P (“Preserve”) key while in the waveform viewer.  This will create a facet named nand2{sim} containing the waveforms.  Open that facet and print it.

3.   Hierarchical Design

 

Now that you have a 2-input NAND gate, you can use it and an inverter to construct a 2-input AND gate. Such hierarchical design is very important in the design of complex systems. Moreover, hierarchical design makes fixing errors much easier.  For example, if you had a chip with a thousand nand gates and made an error in the nand design, you would prefer to only have to fix one nand cell so that all thousand instances of the nand inherit the correction than to need to fix each nand individually.

 

Each schematic has a corresponding symbol, called an icon, used to represent the cell in a higher-level schematic. For example, open the inv{sch} and inv{ic} to see the inverter schematic and icon provided. You will need to create an icon for your 2-input NAND gate. When creating your icon, it is a good idea to keep everything aligned to the 1-l grid, this will make connecting icons simpler and cleaner when you need it for another facet.

 

Open your nand2{sch} and choose View • Make Icon. Electric will create a generic icon based on the exports looking something like Figure 7.  It will drop the icon in the schematic for handy reference; drag the icon away from the transistors so it leaves the schematic readable.

 

Figure 7: nand2{ic} from Make Icon

 

A schematic is easier to read when familiar icons are used instead of generic boxes. Modify the icon to look like Figure 8. Pay attention to the dimensions of the icon; the overall design will look more readable if icons are of consistent sizes.

 

Figure 8: nand2{ic} final version

Click on the icon and choose Facets • Down Hierarchy to drop in to the icon.  The technology will automatically change to artwork. A palette will appear with various shapes. Delete the generic red box but leave the input and output lines.  Turn on the grid.

 

If there is not already a facet center in the facet, place a facet center in the center of the icon using the Edit • New Special Object • Facet Center command.  Drag the facet center where you want it. 

 

The body of the NAND is formed from an open C-shaped polygon, a semicircle, and a small circle. To form the semicircle, place an unfilled circle. Double-click to change its size to 6x6 and to span only 180 degrees of the circle. Use the rotate commands under the Edit menu to rotate the semicircle into place. Place another circle and adjust its size to 1x1. You will need to change the alignment options under the Windows menu to 0.5 to move the circle into place, then set alignment back to 1.  Alternatively, you can press h and use the arrow keys to move objects by ½ grid increments, then press f to return to full grid movement.

 

The opened-polygon shown in Figure 9 can be used to form the C-shaped body. Drop an opened-polygon object. Select it and choose Edit · Special Function · Outline Edit to enter outline edit mode. In this mode, you can use the left button to select and move points and the right button to create points. You should be able to form the shape with four clicks of the right button to define the four vertices. Outline edit mode is not entirely intuitive at first, but you will master it with practice. Choose Edit · Special Function · Exit Outline Edit when you are done. If your shape is incorrect, delete it, drop another opened-polygon, and try again.

 

Figure 9: Opened-Polygon

Electric is finicky about moving the lines with inputs or outputs. If you left-click and drag to select the line along with the input, everything moves as expected. If you try to move only the export name, it won’t move as you might expect. Therefore, make a habit of moving both the line and export simultaneously when editing icons. Note that the line is just an open-polygon and can be shortened if desired by entering Outline Edit mode.

 

Use the Text item in the artwork palette to place a label “nand2” in the center of the icon.

 

4.   Spice transient simulation

 

 

Let’s see if our NAND2 behaves as expected in Spice. Please open a new schematic facet called nand2_tbench.

 

 

Use Edit · New Facet Instance to create (“instantiate”) the nand2{ic} icon or symbol in the testbench schematic.

 

 

Then add two pulse supplies on the 2 inputs (Edit New SPICE Part Pulse) and edit their properties to have the Pulse voltage = 5V and a period of 12ns, and the one of them to have a delay time of 1.5ns.

 

Then add a DC power supply of 5V, and a Vdd symbol (concentric circles), finally name the nets that connect to the inputs A and B, and finally put an Out on the nand2 output.

 

Finally add a transient analysis symbol (Edit New SPICE part Transient analysis) that you should set to 1ns 24ns (step size 1ns and 24ns for 2 periods of the pulse input for an exhaustive set of input combinations). You should also add a Vgnd gnd 0 DC 0 (this removes a slight inconsistency inWinSpice) a .PRINT TRAN V(Out) V(A) V(B) and a .PLOT TRAN V(Out) V(A) V(B)  card, as well as the PMOS and NMOS include model cards. Your schematic should look like this:

 

Finally use SmartSpice as Spice engine and set the flag for global vdd and gnd.

 

Now finally save your SPICE deck and simulate with WinSpice. You should getwaveforms like these:

 

 

You can also zoom into the waveforms (use the mouse) in order to estimate delays and rise and fall times.

 

Congrats, that’s all for Tutorial2!