OverviewProjects
- Low-Power SRAM in Deep-Sub-Micron Processes - funded by C2S2.
- An Ultra-Low Energy Voltage Dithered Processor Core for Medical Sensing Applications - funded by UVA FEST and by the Southeastern Center for Electrical Engineering Education (SCEEE).
- SRAM Circuit Design and Optimization at 45nm and Below - funded by C2S2.
- SRAM for scaled CMOS: The 6T SRAM cell design has been successfully scaled in both bulk and SOI down to the 32/28nm node and has remained for more than a decade the dominant technology development vehicle for advanced CMOS technologies. Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. This effort explores alternate bit cell, SRAM architecture and assist options required for successful migration beyond 32nm, while also examining the trends with scaling.
